About the role
Apex Silicon is the semiconductor discipline of Aether. Specialist agents drive the chip flow end-to-end; the engineer in this role owns one of those agent surfaces (typically physical implementation or verification) and contributes to the others.
Customers in this discipline are running real tape-outs. Mistakes are visible in silicon; the bar is correspondingly high.
What you'll do
- Own one of the chip-design agents end-to-end — design, training, evaluation, customer integration.
- Pair with customer physical-design and verification leads during pilots.
- Co-author the per-release silicon-discipline benchmark papers.
- Maintain the foundry-PDK integration surface for the supported nodes.
Who we're looking for
- Chip-design background. You have shipped silicon — front-end, back-end, or signoff. You know the difference between WNS and TNS without thinking about it.
- Comfortable with the integration between AI and conventional EDA tools.
- Detail-oriented; chip flow does not forgive rough drafts.
Bonus
- Tape-out experience on advanced nodes (5nm or below).
- Background in AI-assisted EDA — design-space exploration, ML-driven PPA.