Aether for semiconductors.
AI that retires the EDA stack.
Aether for semiconductors is what the incumbent EDA stack collapses into when the model is the substrate. Specialist agents drive a complete chip flow — 3DIC architecture, RTL through signoff, multiphysics, manufacturing, silicon lifecycle — and a comprehensive silicon-IP catalog comes with the platform.
- Agents
- 17
- IP blocks
- 107
- Flow
- RTL → GDS
- Tape-outs
- In production
Twelve agents you'd hire. One flow.
EDA is a duopoly of mature stacks with mature lock-in. We don't displace every niche tool, and we don't try. But the spine of the flow — architecture, implementation, verification, signoff, manufacturing — lives behind a single set of contracts.
3DIC architecture
Chiplet partitioning, interposer planning, thermal-aware floorplanning for stacked dies. UCIe and BoW interconnect modelling, die-to-die signal integrity, redistribution-layer routing.
Physical implementation
Synthesis, placement, clock-tree synthesis, routing, congestion management. RTL handed in, GDS handed out. Aware of power, congestion and design-for-manufacturing constraints from the first iteration.
IP integration
Drives a comprehensive silicon-IP catalog. Pin-accurate, timing-aware integration; auto-generated wrappers, integration tests, and back-annotated SDF.
Verification orchestration
Functional verification, formal property checking, emulation orchestration, coverage closure, regression triage. UVM testbench generation from spec.
Multiphysics signoff
Coupled thermal, electromagnetic, mechanical analysis — signoff-grade. IR-drop, EM, ESD, thermal hot-spotting, package warpage.
Manufacturing optimisation
DFM rules, hot-spot detection, yield analysis, OPC, mask synthesis preparation — pinned to your foundry's PDK across the leading-edge nodes.
Silicon lifecycle
Post-tape-out monitoring, in-field telemetry, reliability and aging models. Closes the loop between deployed silicon and the next design.
Processor configuration
ARC-V (RISC-V) and NPU configuration. Per-workload PPA tuning, custom instruction extensions, vector/matrix unit sizing.
SoC interconnect
NoC topology, bus contention, QoS shaping, virtual-channel allocation — for the workload, not for a template.
Security
Side-channel hardening, fault-injection analysis, secure-boot, root-of-trust, key management, post-quantum primitives baked into the flow.
Reliability & aging
BTI, HCI, EM, TDDB, stress-migration — modelled across PVT corners and projected to end-of-life under your workload mix.
AI design-space optimisation
DSO.ai-class search across PPA targets — but driven by Aether, not by a black-box optimiser. Decisions are explainable and reproducible.
From PRD to silicon, under one agent.
Six phases of the chip flow, end-to-end. Every phase is observable, every hand-off is auditable, and every ECO round-trips through the model rather than dying in a folder of TCL.
- 01
Architecture
From PRD to a partitioned, budgeted SoC: block-level area, power and frequency budgets, NoC topology, IP selection, package and 3DIC choices.
- 02
Implementation
RTL coding, synthesis, place-and-route, clock-tree, timing closure. Hand-off to signoff is automated; ECOs round-trip through the model.
- 03
Verification
UVM testbench generation, formal proof of safety properties, gate-level simulation, gate-level coverage, regression triage with explainable failure traces.
- 04
Signoff
Static timing across PVT corners, power and IR analysis, EM, thermal, ESD, package warpage — all driven by the same model that did implementation.
- 05
Tape-out
DFM, hot-spot fix, OPC prep, mask synthesis hand-off to the foundry. The model knows what the foundry rules forbid before you ask.
- 06
Lifecycle
In-field telemetry from deployed silicon flows back into the next design. Reliability models update; the second tape-out is better than the first.
In place of three vendors.
These are the tools in a typical fabless or IDM EDA stack today. Aether for semiconductors replaces the spine and the seat-licensing tax that comes with it. Niches — custom analog cells, foundry-specific signoff — stay where they are.
107 blocks, shipped with the platform.
The IP integration agent stitches these into your floorplan without the per-block licence dance. Each block has a verification suite, a power model, and integration tests that ship with it.
Pinned to real PDKs.
The model is calibrated against the rules and constraints of the foundry node you actually tape out on. Every supported PDK has a validated regression suite.
RTL to signoff, one database.
The EDA stack is a dozen point tools and as many file hand-offs. Aether drives the whole flow from one model and one database — DFM-aware from the first iteration.
Quarters of tape-out cycle, compressed to weeks.
The slowest part of taping out a chip isn't any one solve — it's the script handoffs, the corner sweeps and the ECO loops. Aether collapses each of those into the autonomous agent flow on one database.
vs. a leading commercial EDA flow on the public 7nm predictive PDK. ≤0.4% WNS gap. Reproduction scripts in the research log.
Programme-level compression measured at the first fabless customers. The dominant gain is fewer ECOs and faster signoff closure.
Fabless customers running Aether for semiconductors on the published flow report no incumbent-EDA license consumption for their primary signoff.
Aether is an autonomous chip designer.
Not a chat assistant for your EDA flow — a foundation model that takes a spec and returns a GDS. Plans the floorplan, runs the agents, clears signoff, hands off to the foundry.
- 01
Reads the spec
Ingests the micro-architecture, the power and area budget, the foundry process and your IP catalog. Decomposes the brief into a floorplan-aware study tree.
- 02
Picks the right flow
Knows when synthesis margin is enough and when physical-aware synthesis is required. Knows which library corner pairs with which signoff. The senior physical-design engineer's intuition encoded.
- 03
Runs synthesis, P&R, signoff
Specialist production agents execute the flow as a DAG. Long routing runs check-point. Signoff agents share the same database the placement agent wrote to.
- 04
Validates against signoff
STA, IR, EM, DRC, LVS — all gates the model has to clear before any artefact reaches you. Drift halts the run and surfaces the offending net.
- 05
Writes the signoff pack
Auto-written signoff reports with WNS / TNS distributions, IR-drop maps, EM violations and the GDS hash. Ready for tape-out review.
- 06
Closes the foundry loop
Foundry-pack bundles, abstract-cell hand-off, version-pinned process kits — assembled and signed by the model version. Foundries get a clean drop, not a folder of one-offs.
A foundation model that tapes out, not just suggests RTL — the substrate for general silicon intelligence.
Aether reasons in RTL, logic, timing and physics — the substrate of digital silicon. We are moving toward general intelligence through the disciplines that have to face physical reality. The model that signs off your chip today is the model that designs the next one tomorrow.
Numbers against commercial baselines.
We benchmark against the commercial EDA stacks themselves, on published cases. Reproduction scripts are in the research log.
The work behind this product.
We publish what we learn. The posts below are the substantive notes behind this product — methods, evaluations, case studies.
Bring it to your next tape-out.
Send us the spec and the schedule. We'll show you what Aether does with one block of your real design — under your foundry's PDK.