All researchers
Researcher
Dr. Mateusz Kowalski
Mateusz leads the silicon programme at Apex — RTL synthesis, place-and-route, signoff. His work brings a foundation model into the physical implementation flow that a fab will sign off on. Before Apex, he led EDA platform work at a fabless semiconductor company.
Recent
Recent papers and notes.
A slice of what Mateusz has been writing. External papers link to the research log; internal notes link where we can.
- 01Foundation models for physical implementation (Apex, 2026)
- 02On predictive PDK quality vs foundry PDK (Apex internal, 2025)
- 03ASAP7 PPA closure at iso-area (Apex, 2026)
The open problem
“Where does the model's predicted timing diverge from sign-off timing, and why?”
Interests
- · Foundation-model-driven physical implementation
- · Foundry-pack isolation
- · PPA optimisation across PDK generations
If you work on this — or have a strong view — write to research@apexworldlabs.com. We respond to every researcher inbound.
Work on a problem on this page.
Apex hires small numbers of unusually senior people. If you've worked on the problem the researcher above is open on — write to careers@apexworldlabs.com with a one-page brief.