Aether for semiconductors — timing closure on open RTL-to-GDS benchmarks

Abstract

We characterise Aether for semiconductors' physical-implementation flow on the public open RTL-to-GDS benchmark infrastructure ^[1], comparing against a leading commercial place-and-route + timing-signoff stack at matched cell library, constraints, and target density. On the public 45 nm open-cell-library benchmark suite the flow closes worst-negative-slack within 0.4% of the commercial baseline; on the public 7 nm predictive PDK ^[2] it achieves 1.06× performance at iso-area. We document the methodology, the per-design breakdown, the failure mode (designs with heavy clock-domain crossings), and the reproduction kit.

1. Why this benchmark

Timing closure is the hardest stretch of a chip flow. Every modern EDA stack reports timing-closure quality in its own internal benchmarks, against its own regression suites, with its own choices of constraint and tool-flag tuning. Head-to-head comparison between stacks is correspondingly rare — partly because each vendor's benchmarks are not open, partly because the methodology differences make direct comparison subjective.

The public RTL-to-GDS infrastructure ^[1] solves this. The benchmark designs, the cell libraries, the constraints, the reference scripts and the expected results are all open. Anyone can reproduce. The infrastructure has been used by academic and industrial groups for several years and the methodology is well-understood.

We picked this benchmark because it lets us publish a head-to-head against a commercial baseline that the reader can verify independently. We do not claim every customer workload will look like the public benchmarks; we do claim that the comparison shown here is reproducible.

2. What we ran

Aether for semiconductors' physical-implementation agent took the public 45 nm open-cell-library designs and the public 7 nm predictive PDK ^[2] benchmark suite through synthesis, placement, clock-tree synthesis, global routing and detailed routing. Constraints, library, and target density were held fixed across Aether and the commercial baseline. We did not tune flags for either tool; both used their default protocols.

Result tabulation was performed by an independent reviewer who did not know which tool had produced which result until pass/fail had been recorded — the same blinding protocol we used in our CAE-displacement pilot ^[3]. The reviewer's pass/fail thresholds were the standard ones documented in the published benchmark infrastructure ^[1].

We ran each design three times with independent random seeds and report mean ± standard deviation. Within-seed variance was small (<0.2% on WNS); the headline numbers are robust to the seed choice.

3. Headline numbers

Worst-negative-slack on the public open-cell-library benchmark closes within 0.4% of the commercial baseline at matched density. Total-negative-slack is within 1.0% on the same suite. On the public 7 nm predictive PDK ^[2], at iso-area, Apex Silicon achieves 1.06× the operating frequency of the commercial baseline.

Power and IR-drop signoff agreement is within 2.0% on current density across the published test set. EM signoff agreement is within 1.5%. These are not headline-grade differentiators — both tools produce signoff-grade results — but they indicate that we are not winning on timing at the cost of regression in adjacent signoff dimensions.

4. Per-design breakdown

Performance is consistent across the benchmark suite but not uniform.

• Small synthesisable cores (matrix multipliers, FFT) — Apex Silicon closes 0.6–1.2% tighter WNS.
• Mid-size RISC cores — within 0.3% WNS, with Apex Silicon slightly ahead on dynamic power at iso-frequency.
• DSP blocks with regular structure — Apex Silicon closes 0.8% tighter WNS, owing to better register placement around the multiplier array.
• SoC subsystems with multi-domain clocking — the commercial baseline closes 0.4–0.8% tighter WNS. This is the failure mode discussed in Section 6.
• Memory-controller blocks — within 0.2% WNS; functionally a tie.

5. Where Apex Silicon does well

Designs with regular clocking and balanced fan-out close cleanly. The model's placement decisions produce shorter critical paths than the commercial baseline's greedy heuristics — partly because the model has been trained on the closure patterns of a large body of designs ^[4], partly because the optimisation objective explicitly weights critical-path length rather than treating it as one of several balanced objectives.

Power-aware placement reduces switching activity slightly, which translates into measurable dynamic-power savings at the same frequency. Across the benchmark we observe 1.5–4% dynamic-power reductions at matched performance, depending on the design's switching profile.

Routing congestion is consistently lower at the same density. We attribute this to a better global-routing decision than the standard heuristic, but the mechanism is not fully transparent — the model's planning head learned a strategy we did not explicitly design for.

6. Where the baseline still wins

On designs with heavy clock-domain crossings, the commercial baseline closes WNS by a small but consistent margin — 0.4–0.8% across the affected designs. The mechanism is that our planner sometimes over-commits routing resources to a dominant domain, leaving the crossing-affected paths slack-poor.

We are working on a domain-aware planning head. Preview results on a small internal benchmark suggest we recover the gap; we will publish when the result is robust on the public benchmarks. For customers running designs with heavy multi-domain clocking today, we document this limitation honestly and let them decide; many of our pilot customers in this category have proceeded anyway because the timing gap is within their margin of acceptance.

7. Beyond timing — what we measure but don't headline

Three other dimensions worth a brief mention.

First, turn-around time. Aether for semiconductors' flow completes a full RTL-to-GDS pass on the largest benchmark design in approximately 70% of the commercial baseline's wall-clock at matched signoff quality. This is not the focus of the paper but it matters in production: faster turn-around means more design-space iterations per quarter.

Second, design-rule check (DRC) cleanliness. Both flows produce DRC-clean GDS on the public benchmarks; the rare violations are equal in count and category between the two.

Third, ECO support. Apex Silicon supports incremental engineering-change-order flow at the same fidelity as the commercial baseline. We have not benchmarked this specifically because the public benchmark suite does not include ECO scenarios; production customers exercise this flow regularly and report it as competitive.

8. Limitations

Three meaningful limitations. First, the public RTL-to-GDS benchmark designs are smaller than typical production SoCs; performance characteristics on larger designs may differ, and we report production tape-out results separately in customer case studies. Second, we benchmark against one commercial baseline; other commercial stacks may produce different head-to-head outcomes. Third, the public 7 nm predictive PDK ^[2] is a research artefact rather than a production foundry node; customer designs targeting production nodes are subject to the foundry's actual PDK constraints, which are richer.

Reproducibility: the full reproduction kit — RTL, SDC constraints, library, run scripts, expected results — is open under the Research tier. The runs take roughly four to six hours per design on a 32-core node; nothing exotic is required.

9. Conclusion

Aether for semiconductors' physical-implementation flow closes timing on the public RTL-to-GDS benchmark suite ^[1] within 0.4% WNS of the leading commercial baseline, at 1.06× performance at iso-area on the public 7 nm predictive PDK ^[2]. The flow wins on designs with regular clocking and loses by a small margin on designs with heavy clock-domain crossings; the loss is being addressed on the roadmap. Reproduction is open, and the methodology is verifiable end-to-end.