Background
Helix is a Tier-1 fabless silicon company designing a 4nm SoC for a mobile-class workload. Their existing EDA stack covered the full spine — synthesis, place-and-route, static timing, functional verification, power and IR signoff, DFM and OPC — split across the three established EDA vendors. They had used the stack for three previous tape-outs and were considering renewal across all three.
The challenge
Helix's engineering leadership wanted to consolidate the stack but had not seen credible evidence that an AI-driven flow could tape out functional silicon at advanced nodes. The team was conservative about substituting the spine of the flow without proof from real silicon.
What we did
- Aether for semiconductors' specialist agents drove the full flow: architecture, RTL synthesis, place-and-route, IP integration, verification, multiphysics signoff, manufacturing prep.
- Helix integrated the comprehensive silicon-IP catalog directly — replacing per-block licence agreements with platform-level integration.
- One incumbent stayed for a specific custom-cell flow; everything else moved to Aether over a single tape-out cycle.
- Forward-deployed engineer paired with Helix's physical-design lead for the duration.
The outcome
- First silicon came back functional on the first revision.
- Helix retired the rest of their EDA stack within the quarter.
- Timing closure converged 1.06× faster at iso-area versus the previous flow.
- Power and IR signoff results agreed with the previous tool flow within 2.0% on current-density.
One detail worth calling out
The unexpected win was in IP integration. The comprehensive catalog removed a quarter's worth of per-block licence negotiation. Helix's procurement team was the first to argue for not renewing.