RTL → GDS at 7nm with PPA targets
Compile Verilog to placed-and-routed GDS at a 7nm predictive PDK with PPA targets and DRC clean. Returns the database with a signed manifest.
- Artefact returned
- GDS · timing report · power report · DRC clean
- Typical runtime
- ~4 h wall · 96 CU
- Cost
- ≈ $310 per signoff + Pro seat
The expanded snippet.
The version that lands in production — with the annotations a colleague would want when picking up the work. Copy-paste, swap in your inputs, run.
from apex import Aether
simos = Aether(api_key=os.environ["APEX_API_KEY"])
# Compile Verilog RTL to a placed-and-routed GDS at a 7nm predictive PDK with
# DRC, LVS and antenna enabled. The runtime hands off to placement on
# successful synthesis and emits a signed manifest binding the GDS to the
# model version that produced it.
run = simos.rtl_synthesise(
rtl="s3://my-bucket/cpu_core.v",
pdk="asap7-predictive",
targets={
"freq_mhz": 1800,
"area_um2": 92000,
"power_mw": 380,
},
enable=["dft", "lvs", "drc", "antenna", "density"],
constraints={
"max_fanout": 32,
"max_transition_ns": 0.18,
},
optimisation="aggressive",
)
print(f"WNS = {run.wns_ns:.3f} ns")
print(f"Area = {run.area_um2:.0f} um2")
print(f"Power = {run.power_mw:.0f} mW")
print(f"DRC clean = {run.drc_clean}")
print(f"GDS = {run.gds_uri}")
print(f"Manifest = {run.manifest_uri}")The numbers in this recipe are real.
What we ran. What we used for inputs. Where the reproduction kit lives, and what reproduces within published bounds.
- 01RTL: any Verilog 2005 / SystemVerilog 2017 design. The cookbook repo ships a small open RISC-V core.
- 02PDK: ASAP7 predictive PDK; commercial 7nm and 5nm PDKs supported under foundry-pack isolation.
- 03Reproduces WNS ≤ 0.4% gap vs commercial EDA on the published benchmark.
- 04Wall time scales with gate count; estimate uses ~92k gates.
Make it your workload.
The recipe is a starting point. The four variations below are the ones we get asked about most. Anything else, write to docs@apexworldlabs.com.
- Larger designs: pass partition="auto" and the runtime decomposes the design across compute.
- Foundry PDK: enterprise customers can mount their NDA-protected foundry pack with foundry_pack="...".
- Add IP: include vendor-IP wrappers; the runtime treats them as fixed-cell instances.
- Quick exploration: pass mode="explore" for fast PPA estimates without full signoff.
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Adapt this to your stack.
Swap in your geometry / target / repo and run it. If your workload is novel, send it and we will co-author the recipe with you.